By means of tests of active matrix display panels that operate by liquid crystals or electroluminescence (EL hereafter; for instance, an organic EL or other EL element), circuit tests referred to as array tests are conducted on each pixel of a TFT array wherein each pixel circuit is made in matrix form on a panel.
The present Specification includes both TFT arrays that are subjected to array tests before the liquid crystals or EL elements have been formed or those that are subjected to array tests after the liquid crystals or EL elements have been formed. It is generally preferred that defective products be rejected before the expensive pixels are formed in order to reduce production costs.
Each pixel circuit of the TFT array of a display panel generally comprises a pixel selecting transistor for selecting pixels; a holding capacitor for accumulating voltage supplied to the pixels; and a pixel driving part for driving the pixels in accordance with the supplied voltage.
One array test involves examining the holding properties of the holding capacitor. By means of this test, a predetermined charge is written in the holding capacitor and the charge that remains after a predetermined holding time (generally 16.7 ms of frame time) has elapsed is read. FIGS. 13 and 14 and paragraphs 49 through 55 of Japan Patent Publication 7[1995]-5408, relate to active matrix liquid crystals and show an algorithm for shortening the measurement time of holding capacitor tests on liquid crystal TFT arrays.
On the other hand, the liquid crystals of active matrices of recent years have a shift register that corresponds to both the horizontal and vertical shift registers of a TFT array as referred in Sony, LCX028BMT (4.6 cm (1.8-inch) black-and-white LCD panel) data sheet.
The following is a discussion of the method for measuring the holding capacitor which has been developed by the inventors for a TFT array of an active matrix display panel comprising control lines to a shift register for pixel selection based on the testing method disclosed in FIG. 13 of Japan Patent Publication 7[1995]-5408, FIGS. 13 and 14, paragraphs 49 through 55.
It should be noted that as in Japan Patent Publication 7[1995]-5408, FIGS. 13 and 14, paragraphs 49 through 55, writing time Tw and reading time Tr of the holding capacitor are the same and are represented by τ in this discussion.
As shown in the block diagram in FIG. 10 of a general testing device 1300 assumed by the inventors, a TFT array 1302 comprises an H shift register (horizontal shift register) 1340 for selecting data lines and a V shift register (vertical shift register) 1342 for selecting gate lines, and the pixels (represented by 1356, 1358, and 1360) are selected and tested by these registers. There is a clock terminal (CLK_H 1328, CLK_V 1348) and a pulse input terminal (Start_H 1330, Start_V 1346) at each shift register and these terminals perform the shift operation. An enable terminal (ENB_V) is connected to the V shift register. A charge meter Q 1310 for performing a measurement of electric charges and a variable voltage source 1322 are connected in series to a power source terminal 1324 of the H shift register.
However, as persons skilled in the art can easily understand, Tw and Tr must be the same, because the holding time Th to each pixel in a group that will be written in a lot and be read in a lot must be the same according to the method shown in FIG. 13 of the Japan Patent Publication 7[1995]-5408.
Next, the measuring method by the testing device in FIG. 10 that was assumed by the inventors will be described using the timing chart in FIG. 11. This testing method is the procedure whereby all of the pixels are divided into multiple pixel groups and tests are performed by each pixel group. This discussion focuses on the jth pixel group. After writing, that is, charging to the holding capacitor, first pixel Pj,l for writing time W (that is, Tw in FIG. 13 of Japan Patent Publication 7[1995]-5408) starting from time t10, the charge is read, that is, measured, over reading time R starting from time t13 after holding time H (that is, Th in FIG. 13 of Japan Patent Publication 7[1995]-5408). A1 here is the waiting time during writing for the difference between writing time W and reading time R in order to guarantee holding time H of each pixel.
The number of pixels of each pixel group in the method shown in FIG. 11 becomes a maximum of N=H/R from the relationship between holding time H and reading time R. The total number of pixel groups are assumed M.
Hereafter the ith pixel of the jth pixel group will be represented as Pi,j in the present specification. The term “pixel group” means pixels measured together as one group.
It should be noted that A3 in FIG. 11 is the waiting time, which becomes a fraction due to the relationship between holding time H and reading time R.
When this is applied to FIG. 10, the step is implemented whereby data line Dm is set at writing voltage Vw and writing is performed from the top to the bottom on N number of pixels 1356, 1358, 1360 . . . , while data line Dm is set at reading voltage Vr and reading is performed from the top to the bottom of pixels 1356, 1358, 1360 . . . , wherein holding time H has elapsed, and the holding measurements are studied.
There is a concern that various floating capacities will be present because the circuits are housed in a TFT array. In particular, there is a concern that the charge that has accumulated in these floating capacities between the data lines and other various signal lines once N number of pixels have been written will have an effect in the form of a difference in measurements when the first pixel of the next reading operation is measured.